The invention relates to a method of and apparatus for testing fully differential electrical circuits, to a method of designing such circuits, and to circuits designed by such a method. The invention may be applied to both analogue and digital circuits.
Various analogue design-for-testability and built-in self-test schemes have recently been proposed in the literature. Most of them are based on analogue scan paths, to provide observability of circuit internal nodes. Others use digital to analogue and analogue to digital converters to test the analogue functions from the digital part of the integrated circuit. Some proposals use internal monitors to observe whether relevant analogue parameters are within its tolerance window.
Due to their structure fully differential circuits are inherently redundant circuits. Some self-testing proposals have been made that are based on this property. Those test strategies are based on observing the balance of differential voltage signals at the output of each block in the circuit. The differential voltage signals are transformed into a single ended code that is analysed using a window comparator (checker). An error signal is generated when a code falls outside the valid code space.
It is an object of the invention to enable the provision of a method of and an apparatus for testing fully differential electrical circuits which is comparatively inexpensive to implement.
It is a further object of the invention to enable the provision of a method of designing fully differential electrical circuits which facilitates testing of the circuit designed.
The invention provides a method of testing a fully differential analogue circuit comprising the steps of exciting the circuit with a common mode signal, monitoring two symmetrical branch current signals resulting from the common mode excitation signal, and providing an indication of whether the two branch current signals are correlated.
The invention is based on the realisation that when a fully differential circuit is excited with an input stimulus that is a pure common mode input signal, i.e. no differential mode signal is applied, the circuit response is a common mode output signal as well, and a proper correlation of two branch currents in the symmetrical structure of the circuit is observed.
Each of the branch currents in the symmetrical structure of the fully differential circuit depends on: the common mode input signal, the differential mode input signal, the circuit topology and the bias conditions. Therefore, due to inherent properties of fully differential circuits, when no differential mode input signal is applied both branch currents in the symmetrical structure should be correlated. However, any defect due, for example to the fabrication process that affects the topology of the fully differential circuit, will lead to a mis-correlation of those branch currents, whether in their quiescent component or in their dynamic component.
The indication as to whether the two branch signals are correlated may conveniently be in digital form.
The method may further comprise the steps of:
i) sampling each branch current,
ii) subtracting the sampled current and producing a voltage representing the subtracted currents,
iii) applying the voltage produced in step ii) to a first arrangement to generate a logic 1 when the voltage is equal to or lower than a given value and a logic 0 when the voltage is higher than the given value,
iv) applying the voltage produced in step ii) to a second arrangement to generate a logic 0 when the voltage is equal to or higher than the given value and a logic 1 when the voltage is lower than the given value,
v) exclusively ORing the outputs of the first and second arrangements, and
vi) indicating correlation in dependence on the result of the exclusive ORing.
The given value may be a band of values.
This enables process tolerances to be taken into account so that the monitored currents in the two branches are approximately equal, the permissible deviation between the two currents being defined by the magnitude of the band. It will be appreciated that strict equality of the two branch currents, particularly in the case of analogue circuitry, is unlikely to be achieved due to normal circuit tolerances. Consequently, correct operation of the circuit can be indicated provided that the two currents are correlated within a given tolerance.
The first and second arrangements may be amplifiers having different threshold values.
This provides a convenient method of setting a band of values. The magnitude of the band, or the permitted tolerance, will depend on the difference between the threshold values.
The invention further provides an integrated circuit including a fully differential circuit, the integrated circuit comprising a monitor circuit, said monitor circuit comprising means for sampling currents in symmetrical branches of the differential circuit, means for subtracting the sampled currents and producing an output voltage representing the subtracted currents, a first arrangement for generating a logic 1 when the voltage is equal to or lower than a given value and a logic 0 when the voltage is higher than the given value, a second arrangement for generating a logic 0 when the voltage is equal to or higher than the given value and a logic 1 when the voltage is lower than the given value, an exclusive ORgate having inputs to which the outputs of the first and second arrangements are applied, and an output indicating whether the differential circuit is faulty connected to the output of the exclusive ORgate.
In this way an integrated circuit containing a fully differential circuit can be provided with a self test facility for the fully differential part. This can provide a simplification in the testing of such circuits. That is, by selecting an appropriate part of a circuit and reconfiguring it for test purposes and then monitoring and analysing the branch currents at that part of the circuit the correct functioning of the circuit can be tested for without requiring external test equipment or access to the internal circuitry apart from being able to control the reconfiguration and access the results of the correlation.
The given value may be a band of values. The first and second arrangements may be amplifiers having different threshold values.
This gives a convenient way of achieving a suitable tolerancing of the testing for equality which can take into account normal process variations.
The invention further provides a method of designing for testability fully differential electrical circuits including a test structure comprising the steps of:
i) designing a fully differential circuit to perform a desired function,
ii) selecting one or more parts of the circuit that pass symmetrical currents when a common mode signal is applied to the input of the circuit when the circuit is fault free,
iii) providing switching means for causing said one or more parts to adopt a first configuration to enable the branch currents to be monitored for test purposes and a second configuration for normal circuit operation, and
iv) providing monitoring means for monitoring the branch currents when said one or more parts adopt the first configuration.
This enables the testability of the circuit to be enhanced by providing the means to modify the circuit to perform the test function using the inherent properties of fully differential circuits. Thus, by reconfiguring part of the circuit to enable the branch currents to be monitored, and including a monitoring circuit to enable the branch currents to be monitored and checked for correlation, it becomes possible to detect faults caused during the manufacture of the circuit that affect the circuit topology. The selection of the parts may be carried out using a node impedance analysis to maximise the effect observed.
The invention still further provides a fully differential electrical circuit comprising a monitoring circuit for monitoring the currents in symmetrical branches of the circuit when excited by a common mode input signal, switching means for modifying a part of the circuit for test purposes to enable the current monitoring to take place and to restore said part of the circuit to its normal circuit function at other times, and test means for determining whether the currents in the symmetrical branches are substantially equal under test conditions.
Thus, as manufactured the circuit includes the means for checking its functionality. By applying a common mode signal to its input and activating the test function the circuit is modified to enable symmetrical branch currents to be monitored and their correlation can be used to indicate correct circuit topology. This simplifies the testing of integrated circuits, which with their increasing complexity are becoming more expensive to test to ensure their functionality.